1. Field of the Invention
The present invention relates generally to methods and systems for analyzing circuit architectures, and more particularly, to methods and systems, which determine properties in multilevel interconnection wiring designs for semiconductor devices.
2. Description of the Related Art
To meet demand for increased device density and performance, semiconductor technology which includes a low dielectric constant material (low-k) and interconnection wiring of copper metallurgy is preferable. Such techniques lend themselves to a double or dual damascene method of processing. Because, dry air has the theoretically lowest dielectric constant of one (1), most low-k materials such as, aerogels, hydrogen silsesquioxane (HSQ), oxides (such as, fluorinated oxides), organic polymers (e.g., polyareolyene ether organic dielectrics, such as SiLK™, available from Dow chemical Co., Midland, Mich.), organosilicate glass (e.g., SiCOH deposited by CVD) or porous forms of these compounds are employed.
The high performance interconnection is formed with wirings of high conductivity metallurgies on different levels, insulated from each other with layers of low-k dielectric, and interconnected at desired points. To prevent, or to reduce, the corrosive impurity ingression into the interconnection wiring structure, at least one layer of the top most layer of interconnection wiring is embedded in one or more layers of prior formed standard insulators such as silicon oxide deposited by, e.g., the plasma enhanced chemical vapor deposition (PECVD) using silane (SiH4) or tetraethylorthosilicate (TEOS) precursors. Accordingly, high performance interconnection is comprised of one or more layers of high conductivity copper interconnections, embedded in the low-k dielectric, such as SiLK, and bounded on top and bottom by much denser layers of plasma etched chemical vapor deposited (PECVD) oxide and boro-phosphosilicate glass (BPSG), respectively.
Because of the growing complexity of microcircuitry within existing and future generations of microprocessors, the ability to predict the behavior of circuitry composed of these materials under operational conditions has become more difficult. Techniques that rely on modeling the response of the chip architecture using existing methods are often limited to small sections of the entire chip due to the large number of individual interconnect structures that must be considered.
The determination of the mechanical response of the three-dimensional back end of line (BEOL) architecture on a local scale is difficult using existing tools based on finite element modeling. However, these methods become intractable for the determination of the behavior of the microcircuitry design across the entire chip.